TPU v5p specifications¶
Per-chip and per-pod specifications for TPU v5p.
System architecture¶
Specification |
Value |
Unit |
|---|---|---|
Number of chips per pod |
8960 |
|
Peak compute per chip (BF16) |
459 |
TFLOPs |
Peak compute per chip (FP8) |
459 |
TFLOPs |
HBM capacity per chip |
95 |
GiB |
HBM bandwidth per chip |
2765 |
GBps |
Bidirectional ICI bandwidth per chip |
1200 |
GBps |
DCN bandwidth per chip |
50 |
Gbps |
Interconnect topology |
3D torus |
The largest single slice is 16x16x24 (6144 chips). Multislice training scales to 18432 chips.
Parent topic:TPU v5p