TPU v6e (Trillium)

TPU v6e (Trillium) serves and trains transformer, text-to-image and convolutional models. Each chip has 1 TensorCore and 2 SparseCores, and a pod holds 256 chips in a 2D torus.

Use the specification topic to size a slice, the configurations topic to choose a slice shape, and the VM types topic to see what each VM provides.

• TPU v6e (Trillium) specifications
  Per-chip and per-pod specifications for TPU v6e (Trillium).

• TPU v6e (Trillium) supported configurations
  The slice shapes you can request for TPU v6e (Trillium), and how many chips and hosts each uses.

• TPU v6e (Trillium) VM types
  The VM types available for TPU v6e (Trillium) and the host resources each one provides.

Related information

TPU v6e (Trillium) specifications

TPU v6e (Trillium) supported configurations

TPU v6e (Trillium) VM types

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