TPU v6e (Trillium) specifications¶
Per-chip and per-pod specifications for TPU v6e (Trillium).
System architecture¶
Specification |
Value |
Unit |
|---|---|---|
Peak compute per chip (bf16) |
918 |
TFLOPs |
Peak compute per chip (Int8) |
1836 |
TOPs |
HBM capacity per chip |
32 |
GB |
HBM bandwidth per chip |
1638 |
GBps |
Bidirectional ICI bandwidth per chip |
800 |
GBps |
ICI ports per chip |
4 |
|
DRAM per host |
1536 |
GiB |
Chips per host |
8 |
|
TPU Pod size |
256 |
chips |
Interconnect topology |
2D torus |
|
BF16 peak compute per Pod |
234.9 |
PFLOPs |
All-reduce bandwidth per Pod |
102.4 |
TB/s |
Bisection bandwidth per Pod |
3.2 |
TB/s |
Per-host NIC configuration |
4 x 200 Gbps |
|
Data center network (DCN) bandwidth per Pod |
25.6 |
Tbps |
Parent topic:TPU v6e (Trillium)