TPU7x (Ironwood) specifications¶
Per-chip and per-pod specifications for TPU7x (Ironwood).
System architecture¶
Specification |
Value |
Unit |
|---|---|---|
Chips per pod |
9216 |
|
Peak compute per chip, BF16 |
2307 |
TFLOPs |
Peak compute per chip, FP8 |
4614 |
TFLOPs |
HBM capacity per chip |
192 |
GiB |
HBM bandwidth per chip |
7380 |
GBps |
TensorCores per chip |
2 |
|
SparseCores per chip |
4 |
|
Bidirectional ICI bandwidth per chip |
1200 |
GBps |
DCN bandwidth per chip |
100 |
Gbps |
For the memory layout of each chip, see the memory hierarchy topic.
Parent topic:TPU7x (Ironwood)