TPU v5e specifications¶
Per-chip and per-pod specifications for TPU v5e.
System architecture¶
Specification |
Value |
Unit |
|---|---|---|
Peak compute per chip (bf16) |
197 |
TFLOPs |
Peak compute per chip (Int8) |
393 |
TOPs |
HBM capacity per chip |
16 |
GB |
HBM bandwidth per chip |
800 |
GiBps |
Bidirectional ICI bandwidth per chip |
400 |
GBps |
ICI ports per chip |
4 |
|
DRAM per host |
512 |
GiB |
Chips per host |
8 |
|
TPU Pod size |
256 |
chips |
Interconnect topology |
2D torus |
|
BF16 peak compute per Pod |
50.63 |
PFLOPs |
Per-host NIC configuration |
2 x 100 Gbps |
|
Data center network bandwidth per Pod |
6.4 |
Tbps |
Parent topic:TPU v5e